In general, a semiconductor test system is used to test various semiconductor devices such as a semiconductor memory. For this purpose, a semiconductor test system generates test patterns to apply the test pattern to a device under test. The devices to be tested are becoming to operate at higher speeds, and one of them is a synchronous DRAM.
A synchronous DRAM (SDRAM), unlike a conventional DRAM, is a memory that makes a continuous access of the certain range of addresses possible by itself at high speed by having a special architecture for the continuous access, thus increasing the overall speed of address access. In a typical SDRAM, a read/write rate of 100 Mbytes/sec or greater is possible. For increasing the rate of the continuous access with high speed like this, the read/write of SDRAM is performed in a burst mode. The burst mode is a mode of address access in a memory where data in the same row addresses are read or written continuously by a block of 2, 4, or 8 words or the like. In addition, the access for such words in the block is made by simply providing a start address of the block. Afterward, the remaining addresses are generated automatically in the SDRAM by itself in accordance with its operation mode, i.e., a burst transfer mode, which results in a high speed operation.
An SDRAM has the following characteristics:
(1) Its inside is divided into two banks and the high speed access is made possible by switching the banks. PA1 (2) The addressing and length of a burst during the burst transfer can be switched by a mode register. PA1 (3) The address and data are synchronized with a clock signal.
In addition, there are two methods for the address sequence of the burst transfer; a sequential mode and an interleave mode, which are determined by an address sequence from a CPU. Addresses start address for each burst address sequence method are generated by the following manners in the inside of the SDRAM.
In the sequential mode, the addresses are generated by addition of the burst start address and an output of an internal counter.
Whereas in the interleave mode, the addresses are generated by an exclusive OR of the burst start address and an output of an internal counter.
As a test pattern generator for this type of SDRAM, an example of technology is disclosed in Japanese Patent Application No. 6-73893 Japanese Patent Laid Open Publication No. 7-262799). This technology provides a test pattern generation system for a SDRAM and its method that generates a test pattern for a SDRAM by arranging a dedicated wrap conversion section or providing a method for converting to the wrap addresses. For this purpose, the system is composed of a wrap conversion means which receives two kinds of input data from the pattern generator and outputs the data by converting the data based on predetermined logical circuit information. In addition, the test pattern generation method for an SDRAM in this conventional technology is composed by inputting column address data (for example, Y0-Y2) and a wrap address (for example, Z0-Z2), and outputting an address by converting the column address data and wrap addresses by a predetermined logical formula.
Generally, in order to perform a failure analysis of the internal cell of a device to be tested, it must generate not only an address provided to the memory to be tested, but also addresses for the burst addresses automatically generated in the memory to be tested.
FIG. 8A-8B illustrates the address generation method of the sequential mode and differences in designation of the column addresses by a difference in the burst length in the conventional semiconductor memory test system. The burst address is generated by storing the burst start address in an initial value storage register 31 of Z address and incrementing the start address by an address operation section 32 of Z address. The column address is generated such that Z address (burst addresses) are inserted into the Y address by a formatter 35. The row address is generated by an X address generation section 10. In this way, the testing is performed by assigning the column address by the formatter. Hence, when changing the setting of the burst length, the address assignments for the entire column addresses must be reset. Since the resetting can be done by the formatter during testing, it has a shortcoming of not being able to change the burst length in real time during testing.
FIG. 9 illustrates an address generation method of the interleave mode. A Y address generation section 20 is composed of initial value registers 211, 212, an address operation section 22 and an arithmetic logical operation section 23. In this case, the burst address is generated by executing an exclusive OR of the arithmetic logical operation section 23 of address generator. The burst start address is set in the register 211. The internal counter address of SDRAM is generated by loading the initial value 0 into the register 212 and incrementing the initial value in the operation section 22. The burst address is generated by taking an exclusive OR of the operation section 22 and register 211 in the arithmetic logical operation section 23.
In the aforementioned test methods, the sequential mode and interleave mode must have separate patterns for testing. Hence, the pattern generation for testing presents a problem of becoming cumbersome. This kind of traditional address generators have shortcomings of not being able to change the burst length in real time during testing and change the operation modes of the sequential mode and interleave mode in real time during testing.